A computer system, communication device, and other devices rely on memory to store instructions and data that are processed to perform various tasks. Substantial advances have been made over the years in both the storage capacity and speed of memory devices for use in such applications, however, in some cases the speed of the memory has not kept pace with speed increases achieved with processors or other chips within the same system.
A typical memory contains an array of memory cells connected to each other by row and column lines. Each memory cell typically stores one bit of information and is accessed by a memory address that includes a row address that indexes a row of the memory array and a column address that indexes a column of the memory array. Accordingly, each memory address points to the memory cell at the intersection of the row specified by the row address and the column specified by the column address.
Many applications require a memory to be clocked at its maximum possible cycle time. However, this is extremely difficult to achieve when the maximum possible cycle time is near the system's maximum clock frequency. Such difficulty is due to additional duty cycle margin required for the clock signal as well as the clock jitter and skew margins.
A typical memory receives only a single clock input signal, as illustrated in prior art FIG. 1 and designated at reference numeral 10. Thus the memory speed was limited to the input clock signal frequency. Initially, a solution to that speed limitation was to include multiple clock inputs. This arrangement, as illustrated in one example in prior art FIG. 2A, used a first clock signal 12 (CLKA) to one clock input and a second clock signal 14 (CLKB), inverted from the first, to another clock input of the memory. This technique is often referred to as “clock pumping” or “double pumping” the clock signal, since a logic circuitry 15 and 16 along with clock select signals are employed to selectively pass the two clock signals 12 and 14. Consequently, the memory is effectively clocked at twice the system clock frequency, as illustrated in prior art FIG. 2B, and designated at reference numeral 20.
Double pumping improves the memory speed by operating at a higher frequency, however, double pumping still does not exercise the memory at its maximum possible cycle time since duty cycle margin is compounded due to the inverted clock signal. Thus, there is a need for improved memory circuit designs and solutions that facilitate improved speed.